Conventional metal oxide semiconductor (MOS) transistors are widely used in, for example, integrated circuit memory devices. Typically, a MOS transistor is provided on an active region in an integrated circuit substrate. Furthermore, a MOS transistor typically includes a source, a drain and a gate. The source and drain regions are spaced apart from one another to provide a channel region between the source and the drain regions. An insulated gate including a gate insulating layer, for example, an oxide layer, and a gate electrode, is typically provided on the channel region between the source and drain regions.
A conventional layout of a MOS transistor is discussed in, for example, U.S. Pat. No. 6,223,331 to Juengling, entitled Semiconductor Circuit Design Method for Employing Spacing Constraints and Circuits Thereof. Juengling discusses a method of providing a circuit layout having adequate spacing between transistors. As discussed therein, the spacing of a particular circuit layout may be determined to be outside a particular spacing constraint and additional circuitry may be added to the circuit to bring the spacing of the circuit layout to within the spacing constraint. However, circuits corrected using the methodology discussed in Juengling may have an increased area due to, for example, the inclusion of one or more additional gate lines provided to correct the spacing of the circuit layout. Accordingly, improved devices and methods may be desired that may, for example, reduce the area occupied by the device.